Verilog code for T flip flop

Verilog code for T flip flop

//------------------------------//
// Design Name : T flip flop
//
// Function    : T flip-flop
//
//------------------------------//
module t_ff (
clk   ,
reset ,
data  ,
q      
);

input data, clk, reset ;
output q;

reg q;

always @ ( posedge clk)
if (~reset) begin
  q = 1'b0;
end else if (data) begin    // what will happen data is held high ?
  q = !q;
end

endmodule