Verilog code for JK Flip Flop

Verilog code for JK Flip Flop


//------------------------------
// Design Name : JK flip flop
//
// Function    :JK flip-flop
//
//------------------------------
module JK_ff ( j ,k ,clk ,reset ,q ,qi );

output q ;
output qi ; // inverted output
reg q ;
reg qi ;

input j ;
input k ;
input clk ;
input reset ;
wire j ;
wire k ;
wire clk ;
wire reset ;

always @ (posedge (clk)) begin
if (~reset) begin
q <= 0;
qi <= 1;
end
else begin
if (j!=k) begin
q <= j;
qi <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qi <= ~qi;
end
end
end


endmodule