Verilog code for JK Flip Flop

Verilog code for JK Flip Flop


//------------------------------
// Design Name : JK flip flop
//
// Function    :JK flip-flop
//
//------------------------------
module JK_ff ( j ,k ,clk ,reset ,q ,qi );

output q ;
output qi ; // inverted output
reg q ;
reg qi ;

input j ;
input k ;
input clk ;
input reset ;
wire j ;
wire k ;
wire clk ;
wire reset ;

always @ (posedge (clk)) begin
if (~reset) begin
q <= 0;
qi <= 1;
end
else begin
if (j!=k) begin
q <= j;
qi <= k;
end
else if (j==1 && k==1) begin
q <= ~q;
qi <= ~qi;
end
end
end


endmodule

Verilog code for T flip flop

Verilog code for T flip flop

//------------------------------//
// Design Name : T flip flop
//
// Function    : T flip-flop
//
//------------------------------//
module t_ff (
clk   ,
reset ,
data  ,
q      
);

input data, clk, reset ;
output q;

reg q;

always @ ( posedge clk)
if (~reset) begin
  q = 1'b0;
end else if (data) begin    // what will happen data is held high ?
  q = !q;
end

endmodule

Verilog Code for D flip flop

Verilog Code for D flip flop

//---------------------------------------//
// Design Name : D Flip Flop
//
// Function    : D Flip Flop
//
//----------------------------------------//
module d_ff (
data_in ,
clk    ,
reset , 
q        
);

input data_in, clk, reset ;
output q;
reg q;

always @ ( posedge clk or negedge reset)
begin
if (~reset)

  q = 1'b0;

else

  q = data_in;

end
endmodule