Verilog Code for D flip flop

Verilog Code for D flip flop

//---------------------------------------//
// Design Name : D Flip Flop
//
// Function    : D Flip Flop
//
//----------------------------------------//
module d_ff (
data_in ,
clk    ,
reset , 
q        
);

input data_in, clk, reset ;
output q;
reg q;

always @ ( posedge clk or negedge reset)
begin
if (~reset)

  q = 1'b0;

else

  q = data_in;

end
endmodule