Verilog code for Generation of Grey Code

// Verilog code for Generation of Grey Code


module gray_code(q,reset,clock,q_gray);
input [3:0]q;
input reset,clock;
output [3:0] q_gray;
wire reset,clock;
reg [3:0] q,q_gray;

assign q_gray={q[3],q[3]^q[2],q[2]^q[1],q[1]^q[0]};


always @(negedge reset or posedge clock)
begin
  if(~reset)
    q<=0;
  else
   q<=q+1'b1;
end

endmodule