Verilog code for serial to parallel data converter

Verilog code for serial to parallel data converter

`timescale 1 ns /1 ps
module deserial (clk, reset, serial_data_in,parallel_data_out);
input clk;
input reset;

input serial_data_in;
output reg [7:0] parallel_data_out;
always @ ( posedge clk or negedge reset)
begin
  if (!reset)
    parallel_data_out <= 8'b0;
  else
     parallel_data_out[7 :0] <= {parallel_data_out[6:0],serial_data_in};
end
endmodule

Verilog code for parallel to serial converter

Verilog code for 8 bit parallel to serial converter ( Parallel Data In and Serial Data Out)

`timescale 1 ns /1 ps

module serial (clk, reset, loaden_o, serdes_factor,serial_data_out,parallel_data_in);

input clk;

input reset;

input loaden_o;
input serdes_factor;

input [7:0] parallel_data_in;

output reg serial_data_out;

reg [7:0] sft_reg;

reg [2:0] count_ps;

always @ ( posedge clk or negedge reset)

begin

  if (!reset)

  begin
  sft_reg  =8'b0;

  count_ps = 'b0;

  end

else

begin  if(loaden_o == 1'b1)

      sft_reg = parallel_data_in;

     else

     begin

      serial_data_out = sft_reg[0];

      if (serdes_factor == count_ps)

      count_ps =1'b0 ;

      else 

      begin 

      sft_reg = {sft_reg,sft_reg[7:1]};

      count_ps = count_ps +1;

      end

     end

end

end

endmodule


If you see the code you will find  hardware will be made by a multiplexer and a binary counter.